Toyoda Gosei has developed a semiconductor device with reduced contact resistance in the body electrode without affecting channel mobility. The device features a unique two-layer p-type structure and a recess for improved performance. GlobalData’s report on Toyoda Gosei gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Toyoda Gosei, Passive safety systems was a key innovation area identified from patents. Toyoda Gosei's grant share as of May 2024 was 43%. Grant share is based on the ratio of number of grants to total number of patents.
Semiconductor device with reduced contact resistance and high channel mobility
A recently granted patent (Publication Number: US12002853B2) discloses a semiconductor device in the form of a transistor, utilizing a semiconductor layer made of Group III nitride semiconductor or gallium oxide-based semiconductor. The device features a unique structure with a trench containing a gate electrode covered by a gate insulating film, along with layers of different conductivity types (n-type and p-type) deposited in a specific sequence. A key aspect of the invention is the presence of a recess that extends from the surface to the p-type layer, with a body electrode in contact with the exposed p-type layer at the bottom of the recess. The p-type layer itself consists of multiple sub-layers with varying acceptor concentrations, ensuring optimal performance of the transistor. Additionally, the configuration of the layers and the recess depth play a crucial role in defining the channel region of the transistor, enhancing its functionality.
Furthermore, the patent includes specific details regarding the thickness and acceptor concentration of the various layers within the semiconductor device. For instance, the second p-type layer is required to have a thickness ranging from 0.05 µm to 0.2 µm, with an acceptor concentration falling within the range of 1×10^19/cm^3 to 1×10^20/cm^3. The depth of the recess is carefully determined to ensure the appropriate thickness of the second p-type layer in the region under the recess. Other parameters such as the thickness of the first p-type layer, the range of acceptor concentration for different layers, and the distance between certain components are also specified in the patent claims. Overall, the disclosed semiconductor device represents a significant advancement in transistor technology, particularly in the realm of vertical semiconductor devices with a trench gate structure, offering improved performance and efficiency in various applications.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
