Varroc Engineering has been granted a patent for a monitoring circuit and method for function monitoring. The circuit includes multiple subassemblies that detect and analyze the frequency range of a status signal from a digital circuit. The method compares the frequency of the status signal with predetermined cutoff frequencies to determine the functional reliability of the digital circuit. GlobalData’s report on Varroc Engineering gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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Monitoring circuit for function monitoring of a digital circuit
A recently granted patent (Publication Number: US11656276B2) describes a monitoring circuit and method for monitoring the proper function of a digital circuit, specifically a microprocessor. The monitoring circuit includes multiple subassemblies and semiconductor switches to ensure accurate monitoring.
The monitoring circuit consists of a first subassembly that receives a status signal from the digital circuit within a predetermined frequency range. This subassembly includes high-pass filters and semiconductor switches to process the input signal. A second subassembly implements a logical signal combination using a logical XOR circuit and a third semiconductor switch. The third subassembly generates a delayed output signal representing a functional reliability signal indicating the proper function of the digital circuit.
The second subassembly, as described in claim 2, includes a logical XOR circuit that receives output signals from the first and second semiconductor switches of the first subassembly. The output of the logical XOR circuit is connected in series with a third semiconductor switch.
The third subassembly, as mentioned in claim 3, includes a fourth semiconductor switch connected to the output of the third semiconductor switch. Additionally, a fifth semiconductor switch receives an input signal from the output of the fourth semiconductor switch and generates the functional reliability signal at its output.
To ensure accurate monitoring, claim 4 states that a time delay device is arranged between the output of the fourth semiconductor switch and the input of the fifth semiconductor switch. This time delay device provides a specified time delay for turn-on and turn-off signals generated by the fourth semiconductor switch.
The method described in the patent involves receiving a square-wave status signal from the microprocessor and comparing its frequency with predetermined cutoff frequencies. Based on this comparison, a functional reliability signal is generated. When the frequency of the status signal falls within the predetermined frequency range, the functional reliability signal has a first voltage level. Conversely, when the frequency is outside the range, the functional reliability signal has a second voltage level.
The method further involves filtering the received square-wave status signal using high-pass filters with specific cutoff frequencies, as mentioned in claim 8. The filtered signals are then logically XOR-linked, inverted, and subjected to a time delay before being outputted as the functional reliability signal.
Overall, this patent presents a monitoring circuit and method that can effectively monitor the proper function of a digital circuit, particularly a microprocessor, by analyzing the frequency of the status signal and generating a functional reliability signal based on predetermined voltage levels.
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